The present inventive concept relates to a method for verifying a layout designed for a semiconductor integrated circuit, to a computer system for performing the same, and to a method of manufacturing a semiconductor device conforming to a specified layout.
Patterns of semiconductor devices become finer as the integration of semiconductor devices is increased, i.e., as the devices are scaled down, but there is a limitation to the extent to which patterns can be made finer due to technical limits of processes for fabricating semiconductor devices. If these limits are exceeded as can occur when fabricating a semiconductor integrated circuit to a computer designed layout of the circuit, defects (e.g., a bridge) can occur in patterns formed on a wafer.